? semiconductor components industries, llc, 2000 november, 2000 rev. 1 1 publication order number: mtp10n10e/d mtp10n10e preferred device power mosfet 10 amps, 100 volts nchannel to220 this power mosfet is designed to withstand high energy in the avalanche and commutation modes. the energy efficient design also offers draintosource diodes with fast recovery times. designed for low voltage, high speed switching applications in power supplies, converters and pwm motor controls, these devices are particularly well suited for bridge circuits where diode speed and commutating safe operating area are critical, and offer additional safety margin against unexpected voltage transients. ? internal sourcetodrain diode designed to replace external zener transient suppressor absorbs high energy in the avalanche mode unclamped inductive switching (uis) energy capability specified at 100 c ? commutating safe operating area (csoa) specified for use in half and full bridge circuits ? sourcetodrain diode recovery time comparable to a discrete fast recovery diode ? diode is characterized for use in bridge circuits maximum ratings (t c = 25 c unless otherwise noted) rating symbol value unit drainsource voltage v dss 100 vdc draingate voltage (r gs = 1.0 m w ) v dgr 100 vdc gatesource voltage v gs 20 vdc drain current continuous drain current pulsed i d i dm 10 25 adc total power dissipation derate above 25 c p d 75 0.6 watts w/ c operating and storage temperature range t j , t stg 65 to 150 c thermal resistance junction to case junction to ambient r q jc r q ja 1.67 62.5 c/w maximum lead temperature for soldering purposes, 1/8 from case for 5 seconds t l 275 c 10 amperes 100 volts r ds(on) = 250 m w device package shipping ordering information mtp10n10e to220ab 50 units/rail to220ab case 221a style 5 1 2 3 4 http://onsemi.com nchannel d s g marking diagram & pin assignment mtp10n10e = device code ll = location code y = year ww = work week mtp10n10e llyww 1 gate 3 source 4 drain 2 drain preferred devices are recommended choices for future use and best overall value.
mtp10n10e http://onsemi.com 2 electrical characteristics (t c = 25 c unless otherwise noted) characteristic symbol min max unit off characteristics drainsource breakdown voltage (v gs = 0, i d = 0.25 ma) v (br)dss 100 vdc zero gate voltage drain current (v ds = rated v dss , v gs = 0) (v ds = 0.8 rated v dss , v gs = 0, t j = 125 c) i dss 10 80 m a gatebody leakage current, forward (v gsf = 20 vdc, v ds = 0) i gssf 100 nadc gatebody leakage current, reverse (v gsr = 20 vdc, v ds = 0) i gssr 100 nadc on characteristics (note 1.) gate threshold voltage (v ds = v gs , i d = 1.0 ma) t j = 100 c v gs(th) 2.0 1.5 4.5 4.0 vdc static drainsource onresistance (v gs = 10 vdc, i d = 5.0 adc) r ds(on) 0.25 ohm drainsource onvoltage (v gs = 10 v) (i d = 10 adc) (i d = 5.0 adc, t j = 100 c) v ds(on) 2.7 2.4 vdc forward transconductance (v ds = 15 v, i d = 5.0 a) g fs 4.0 mhos draintosource avalanche characteristics unclamped draintosource avalanche energy see figures 14 and 15 (i d = 25 a, v dd = 25 v, t c = 25 c, single pulse, nonrepetitive) (i d = 10 a, v dd = 25 v, t c = 25 c, p.w. 200 m s, duty cycle 1%) (i d = 4.0 a, v dd = 25 v, t c = 100 c, p.w. 200 m s, duty cycle 1%) w dsr 60 100 40 mj dynamic characteristics input capacitance (v ds = 25 v, v gs = 0, c iss 600 pf output capacitance (v ds = 25 v , v gs = 0 , f = 1.0 mhz) sfi 16 c oss 400 reverse transfer capacitance ) see figure 16 c rss 100 switching characteristics (note 1.) (t j = 100 c) turnon delay time t d(on) 50 ns rise time (v dd = 25 v, i d = 5.0 a, r g =50 w ) t r 80 turnoff delay time r g = 50 w ) see figure 9 t d(off) 100 fall time see figure 9 t f 80 total gate charge (v ds = 0.8 rated v dss , q g 15 (typ) 30 nc gatesource charge (v ds = 0 . 8 rated v dss , i d = rated i d , v gs = 10 v) sfi 17d18 q gs 8.0 (typ) gatedrain charge ddgs ) see figures 17 and 18 q gd 7.0 (typ) sourcedrain diode characteristics (note 1.) forward onvoltage (i rtdi v sd 1.4 (typ) 1.7 vdc forward turnon time (i s = rated i d v gs = 0 ) t on limited by stray inductance reverse recovery time v gs = 0) t rr 70 (typ) ns internal package inductance internal drain inductance (measured from the contact screw on tab to center of die) (measured from the drain lead 0.25 from package to center of die) l d 3.5 (typ) 4.5 (typ) nh internal source inductance (measured from the source lead 0.25 from package to source bond pad) l s 7.5 (typ) 1. pulse test: pulse width 300 m s, duty cycle 2.0%.
mtp10n10e http://onsemi.com 3 typical electrical characteristics v ds , drain-to-source voltage (volts) figure 1. onregion characteristics t j , junction temperature ( c) figure 2. gatethreshold voltage variation with temperature v gs , gate-to-source voltage (volts) figure 3. transfer characteristics t j , junction temperature ( c) figure 4. breakdown voltage variation with temperature i d , drain current (amps) figure 5. onresistance versus drain current t j , junction temperature ( c) figure 6. onresistance variation with temperature r ds(on) , drain-to-source resistance (ohms) r ds(on) , drain-to-source resistance (normalized) i d , drain current (amps) v gs(th) , gate threshold voltage (normalized) v br(dss) , drain-to-source breakdown voltage (normalized) 20 16 12 8 4 20 16 12 8 4 0 1.2 1.1 1 0.9 0.8 -50 -25 0 25 50 75 100 125 150 20 16 12 8 4 0 10 8 6 4 2 0 2 1.6 1.2 0.8 0.4 0 -50 0 50 100 150 200 0.5 0.4 0.3 0.2 0.1 10 8 6 4 2 0 2 1.6 1.2 0.8 0.4 0 -50 0 50 100 150 t j = 25 c 8 v 7 v 6 v 5 v v ds = v gs i d = 1 ma v ds = 15 v t j = -55 c +25 c 100 c v gs = 0 v i d = 0.25 ma t j = 100 c 25 c -55 c v gs = 10 v v gs = 10 v i d = 5 ma i d , drain current (amps) v gs = 10 v 4 v 0.7 v ds = 10 v 200
mtp10n10e http://onsemi.com 4 safe operating area information i d , drain current (amps) i d , drain current (amps) v ds , drain-to-source voltage (volts) figure 7. maximum rated forward biased safe operating area v ds , drain-to-source voltage (volts) figure 8. maximum rated switching safe operating area 020406080 0 40 100 r ds(on) limit thermal limit package limit 10 v gs = 20 v single pulse t c = 25 c 1 1 30 dc 10 m s 1 ms 10 ms 30 10 100 20 10 3 0.3 100 m s t j 150 c forward biased safe operating area the fbsoa curves define the maximum draintosource voltage and drain current that a device can safely handle when it is forward biased, or when it is on, or being turned on. because these curves include the limitations of simultaneous high voltage and high current, up to the rating of the device, they are especially useful to designers of linear systems. the curves are based on a case temperature of 25 c and a maximum junction temperature of 150 c. limitations for repetitive pulses at various case temperatures can be determined by using the thermal response curves. on semiconductor application note, an569, atransient thermal resistancegeneral data and its useo provides detailed instructions. switching safe operating area the switching safe operating area (soa) of figure 8 is the boundary that the load line may traverse without incurring damage to the mosfet. the fundamental limits are the peak current, i dm and the breakdown voltage, v (br)dss . the switching soa shown in figure 8 is applicable for both turnon and turnoff of the devices for switching times less than one microsecond. the power averaged over a complete switching cycle must be less than: t j(max) t c r q jc figure 9. resistive switching time versus gate resistance t, time (ns) r g , gate resistance (ohms) v dd = 25 v i d = 5 a v gs = 10 v t j = 25 c t f t r t d(off) t d(on) 1k 1 1k 1 2 3 5 7 10 20 30 50 70 100 200 300 500 2 3 5 10 20 30 50 100 200 300 500
mtp10n10e http://onsemi.com 5 figure 10. thermal response r(t), transient thermal resistance (normalized) r q jc (t) = r(t) r q jc r q jc = 1.67 c/w max d curves apply for power pulse train shown read time at t 1 t j(pk) - t c = p (pk) r q jc (t) p (pk) t 1 t 2 duty cycle, d = t 1 /t 2 t, time (ms) 1 0.01 d = 0.5 0.05 0.01 single pulse 0.01 0.03 0.02 0.05 0.1 0.2 0.3 0.5 0.02 0.05 0.1 0.2 0.5 1 2 5 10 20 50 100 200 500 10 0 0.7 0.07 0.03 0.3 3 30 300 0.1 0.2 commutating safe operating area (csoa) the commutating safe operating area (csoa) of figure 12 defines the limits of safe operation for commutated source-drain current versus re-applied drain voltage when the source-drain diode has undergone forward bias. the curve shows the limitations of i fm and peak v ds for a given rate of change of source current. it is applicable when waveforms similar to those of figure 11 are present. full or half-bridge pwm dc motor controllers are common applications requiring csoa data. device stresses increase with increasing rate of change of source current so di s /dt is specified with a maximum value. higher values of di s /dt require an appropriate derating of i fm , peak v ds or both. ultimately di s /dt is limited primarily by device, package, and circuit impedances. maximum device stress occurs during t rr as the diode goes from conduction to reverse blocking. v ds(pk) is the peak draintosource voltage that the device must sustain during commutation; i fm is the maximum forward source-drain diode current just prior to the onset of commutation. v r is specified at 80% of v (br)dss to ensure that the csoa stress is maximized as i s decays from i rm to zero. r gs should be minimized during commutation. t j has only a second order effect on csoa. stray inductances in on semiconductor's test circuit are assumed to be practical minimums. dv ds /dt in excess of 10 v/ns was attained with di s /dt of 400 a/ m s. figure 11. commutating waveforms 15 v v gs 0 90% i fm dl s /dt i s 10% t rr i rm t on v ds v f v dsl dv ds /dt v ds(pk) max. csoa stress area v r 0.25 i rm
mtp10n10e http://onsemi.com 6 figure 12. commutating safe operating area (csoa) 020406080 30 25 20 15 0 10 v ds , draintosource voltage (volts) + + - figure 13. commutating safe operating area test circuit v r v gs i fm 20 v r gs dut i s l i v r = 80% of rated v ds v dsl = v f + l i ? dl s /dt + - di s /dt 400 a/ m s 100 120 i s , source current (amps) 5 figure 14. unclamped inductive switching test circuit figure 15. unclamped inductive switching waveforms t l v ds i d v dd t p v (br)dss v dd i d(t) c 4700 m f 250 v r gs 50 w i o v ds(t) t, (time) w dsr 1 2 li o 2 v (br)dss v (br)dss v dd v ds
mtp10n10e http://onsemi.com 7 gate-to-source or drain-to-source voltage (volts) figure 16. capacitance variation c, capacitance (pf) v gs v ds 0 c iss c oss c rss c iss 1250 1000 750 500 30 20 10 0 10 20 figure 17. gate charge versus gatetosource voltage q g , total gate charge (nc) 10 0 04 8 6 4 2 8121620 250 figure 18. gate charge test circuit v in 15 v 100 k 47 k 2n3904 2n3904 1 ma +18 v v dd 10 v 100 k 0.1 m f 100 ferrite bead dut same device type as dut v in = 15 v pk ; pulse width 100 m s, duty cycle 10% t j = 25 c 47 k v ds = 30 v 50 v v gs , gate-to-source voltage (volts) 80 v t j = 25 c i d = rated i d c oss
mtp10n10e http://onsemi.com 8 package dimensions to220 threelead to220ab case 221a09 issue aa style 5: pin 1. gate 2. drain 3. source 4. drain notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: inch. 3. dimension z defines a zone where all body and lead irregularities are allowed. dim min max min max millimeters inches a 0.570 0.620 14.48 15.75 b 0.380 0.405 9.66 10.28 c 0.160 0.190 4.07 4.82 d 0.025 0.035 0.64 0.88 f 0.142 0.147 3.61 3.73 g 0.095 0.105 2.42 2.66 h 0.110 0.155 2.80 3.93 j 0.018 0.025 0.46 0.64 k 0.500 0.562 12.70 14.27 l 0.045 0.060 1.15 1.52 n 0.190 0.210 4.83 5.33 q 0.100 0.120 2.54 3.04 r 0.080 0.110 2.04 2.79 s 0.045 0.055 1.15 1.39 t 0.235 0.255 5.97 6.47 u 0.000 0.050 0.00 1.27 v 0.045 --- 1.15 --- z --- 0.080 --- 2.04 b q h z l v g n a k f 123 4 d seating plane t c s t u r j on semiconductor and are trademarks of semiconductor components industries, llc (scillc). scillc reserves the right to make changes without further notice to any products herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. atypicalo parameters which may be provided in scill c data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. all operating parameters, including atypicalso must be validated for each customer application by customer's technical experts. scillc does not convey any license under its patent rights nor the rights of others. scillc products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body , or other applications intended to support or sustain life, or for any other application in which the failure of the scillc product could create a sit uation where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized application, buyer shall indemnify and hold scillc and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthori zed use, even if such claim alleges that scillc was negligent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative action employer. publication ordering information central/south america: spanish phone : 3033087143 (monfri 8:00am to 5:00pm mst) email : onlitspanish@hibbertco.com tollfree from mexico: dial 018002882872 for access then dial 8662979322 asia/pacific : ldc for on semiconductor asia support phone : 3036752121 (tuefri 9:00am to 1:00pm, hong kong time) toll free from hong kong & singapore: 00180044223781 email : onlitasia@hibbertco.com japan : on semiconductor, japan customer focus center 4321 nishigotanda, shinagawaku, tokyo, japan 1410031 phone : 81357402700 email : r14525@onsemi.com on semiconductor website : http://onsemi.com for additional information, please contact your local sales representative. mtp10n10e/d north america literature fulfillment : literature distribution center for on semiconductor p.o. box 5163, denver, colorado 80217 usa phone : 3036752175 or 8003443860 toll free usa/canada fax : 3036752176 or 8003443867 toll free usa/canada email : onlit@hibbertco.com fax response line: 3036752167 or 8003443810 toll free usa/canada n. american technical support : 8002829855 toll free usa/canada europe: ldc for on semiconductor european support german phone : (+1) 3033087140 (monfri 2:30pm to 7:00pm cet) email : onlitgerman@hibbertco.com french phone : (+1) 3033087141 (monfri 2:00pm to 7:00pm cet) email : onlitfrench@hibbertco.com english phone : (+1) 3033087142 (monfri 12:00pm to 5:00pm gmt) email : onlit@hibbertco.com european tollfree access*: 0080044223781 *available from germany, france, italy, uk, ireland
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